Synopsis: Important: libvirt security update
Advisory ID:       SLSA-2019:1180-1
Issue Date:        2019-05-14
CVE Numbers:       CVE-2018-12126
                   CVE-2018-12130
                   CVE-2018-12127
                   CVE-2019-11091
--

Security Fix(es):

* A flaw was found in the implementation of the "fill buffer", a mechanism
used by modern CPUs when a cache-miss is made on L1 CPU cache. If an
attacker can generate a load operation that would create a page fault, the
execution will continue speculatively with incorrect data from the fill
buffer while the data is fetched from higher level caches. This response
time can be measured to infer data in the fill buffer. (CVE-2018-12130)

* Modern Intel microprocessors implement hardware-level micro-
optimizations to improve the performance of writing data back to CPU
caches. The write operation is split into STA (STore Address) and STD
(STore Data) sub-operations. These sub-operations allow the processor to
hand-off address generation logic into these sub-operations for optimized
writes. Both of these sub-operations write to a shared distributed
processor structure called the 'processor store buffer'. As a result, an
unprivileged attacker could use this flaw to read private data resident
within the CPU's processor store buffer. (CVE-2018-12126)

* Microprocessors use a load port subcomponent to perform load operations
from memory or IO. During a load operation, the load port receives data
from the memory or IO subsystem and then provides the data to the CPU
registers and operations in the CPUs pipelines. Stale load operations
results are stored in the 'load port' table until overwritten by newer
operations. Certain load-port operations triggered by an attacker can be
used to reveal data about previous stale requests leaking data back to the
attacker via a timing side-channel. (CVE-2018-12127)

* Uncacheable memory on some microprocessors utilizing speculative
execution may allow an authenticated user to potentially enable
information disclosure via a side channel with local access.
(CVE-2019-11091)
--

SL6
  x86_64
    libvirt-0.10.2-64.el6_10.1.x86_64.rpm
    libvirt-client-0.10.2-64.el6_10.1.i686.rpm
    libvirt-client-0.10.2-64.el6_10.1.x86_64.rpm
    libvirt-debuginfo-0.10.2-64.el6_10.1.i686.rpm
    libvirt-debuginfo-0.10.2-64.el6_10.1.x86_64.rpm
    libvirt-python-0.10.2-64.el6_10.1.x86_64.rpm
    libvirt-devel-0.10.2-64.el6_10.1.i686.rpm
    libvirt-devel-0.10.2-64.el6_10.1.x86_64.rpm
    libvirt-lock-sanlock-0.10.2-64.el6_10.1.x86_64.rpm
  i386
    libvirt-0.10.2-64.el6_10.1.i686.rpm
    libvirt-client-0.10.2-64.el6_10.1.i686.rpm
    libvirt-debuginfo-0.10.2-64.el6_10.1.i686.rpm
    libvirt-python-0.10.2-64.el6_10.1.i686.rpm
    libvirt-devel-0.10.2-64.el6_10.1.i686.rpm

- Scientific Linux Development Team

SciLinux: SLSA-2019-1180-1 Important: libvirt on SL6.x i386/x86_64

A flaw was found in the implementation of the "fill buffer", a mechanism used by modern CPUs when a cache-miss is made on L1 CPU cache

Summary

Important: libvirt security update



Security Fixes

* A flaw was found in the implementation of the "fill buffer", a mechanism used by modern CPUs when a cache-miss is made on L1 CPU cache. If an attacker can generate a load operation that would create a page fault, the execution will continue speculatively with incorrect data from the fill buffer while the data is fetched from higher level caches. This response time can be measured to infer data in the fill buffer. (CVE-2018-12130)
* Modern Intel microprocessors implement hardware-level micro- optimizations to improve the performance of writing data back to CPU caches. The write operation is split into STA (STore Address) and STD (STore Data) sub-operations. These sub-operations allow the processor to hand-off address generation logic into these sub-operations for optimized writes. Both of these sub-operations write to a shared distributed processor structure called the 'processor store buffer'. As a result, an unprivileged attacker could use this flaw to read private data resident within the CPU's processor store buffer. (CVE-2018-12126)
* Microprocessors use a load port subcomponent to perform load operations from memory or IO. During a load operation, the load port receives data from the memory or IO subsystem and then provides the data to the CPU registers and operations in the CPUs pipelines. Stale load operations results are stored in the 'load port' table until overwritten by newer operations. Certain load-port operations triggered by an attacker can be used to reveal data about previous stale requests leaking data back to the attacker via a timing side-channel. (CVE-2018-12127)
* Uncacheable memory on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. (CVE-2019-11091)
SL6 x86_64 libvirt-0.10.2-64.el6_10.1.x86_64.rpm libvirt-client-0.10.2-64.el6_10.1.i686.rpm libvirt-client-0.10.2-64.el6_10.1.x86_64.rpm libvirt-debuginfo-0.10.2-64.el6_10.1.i686.rpm libvirt-debuginfo-0.10.2-64.el6_10.1.x86_64.rpm libvirt-python-0.10.2-64.el6_10.1.x86_64.rpm libvirt-devel-0.10.2-64.el6_10.1.i686.rpm libvirt-devel-0.10.2-64.el6_10.1.x86_64.rpm libvirt-lock-sanlock-0.10.2-64.el6_10.1.x86_64.rpm i386 libvirt-0.10.2-64.el6_10.1.i686.rpm libvirt-client-0.10.2-64.el6_10.1.i686.rpm libvirt-debuginfo-0.10.2-64.el6_10.1.i686.rpm libvirt-python-0.10.2-64.el6_10.1.i686.rpm libvirt-devel-0.10.2-64.el6_10.1.i686.rpm
- Scientific Linux Development Team

Severity
Advisory ID: SLSA-2019:1180-1
Issued Date: : 2019-05-14
CVE Numbers: CVE-2018-12126
CVE-2018-12130
CVE-2018-12127

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